In the field of semiconductor device manufacturing, it is well known to couple one area of the device to another area of the device through bitlines and bitline contacts. The bitline contacts are typically formed between MOSFETs in the array device regions and they are configured in such a manner that one end of the bitline contact is in electrical contact with a diffusion region formed in the substrate and the other end of the bitline contact is in electrical contact with the bitline. The bitline, on the other hand, is used to provide electrical contact with other device regions present in the structure, or alternatively, with other devices which are external to the semiconductor device.
Typically, prior art bitlines and bitline contacts are formed utilizing two separate and distinct masking steps.
The first masking step forms the bitline contact between MOSFETs, while a separate and distinct masking step is used in defining the region in which the bitline will be formed. The use of prior art methods for fabricating bitlines and bitline contacts adds extra processing steps and costs to the overall manufacturing process.
Moreover, prior art methods of separately preparing bitlines and bitline contacts do not provide a semiconductor structure in which the bitline contact is significantly self-aligned to the bitline. Instead, the separate masking steps may cause a slight misalignment between the bitline and bitline contact. This slight misalignment provided by prior art methods may lead to increased parasitic capacitance, noise and eventually device failures.
in view of the above problems with prior art processes of separately forming bitlines and bitline contacts, there is a continued need for providing a new and improved method in which the bitlines and bitline contacts can be fabricated from a single masking process in which linespace patterns are used in defining both the bitlines and the bitline contacts.